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Cypress Semiconductor /psoc63 /CSD0 /ADC_RES

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Interpret as ADC_RES

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0VIN_CNT0 (HSCMP_POL)HSCMP_POL 0 (ADC_OVERFLOW)ADC_OVERFLOW 0 (ADC_ABORT)ADC_ABORT

Description

ADC measurement

Fields

VIN_CNT

Count to source/sink Cref1 + Cref2 from Vin to Vrefhi.
HSCMP_POL

Polarity used for IDACB for this last ADC result, 0= source, 1= sink
ADC_OVERFLOW

This flag is set when the ADC counter overflows. This is an indication to the firmware that the IDACB current level is too low.
ADC_ABORT

This flag is set when the ADC sequencer was aborted before tripping HSCMP.

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data